1. Field of the Invention
This invention relates to semiconductor devices and more particularly to methuds and apparatus for protection of semiconductor devices from electrostatic discharge damage.
2. Description of Related Art
ESD (electrostatic discharge) damage has become one of the main reliability concerns on the IC (integrated circuit) products. Especially, while the CMOS technology is developed into the deep-submicron regime, the scaled-down MOS devices and thinner gate oxide become more vulnerable to ESD stress. For general industrial specification, the input and output pins of the IC products have to sustain the human-body-model ESD stress of above 2000V. Thus, the ESD protection circuits have to be placed around the input and output pads of the IC devices to protect the IC devices against the ESD damage.
In the deep-submicron CMOS technology, the short-channel NMOS device (also PMOS device) has the Lightly Doped Drain (LDD) structure to overcome the hot-carrier effect. The LDD structure also generates a peak structure at the drain region, which closes to the surface channel. When such an NMOS device is stressed by a positive ESD voltage, the ESD current is focused and discharged through the LDD peak of the NMOS device structure. Because the LDD peak is the nearest region close to the grounded source, the first breakdown on the drain of the NMOS device happens at this LDD peak region. So, the LDD region with a far shallower junction depth is easily damaged by the ESD current to cause a far lower ESD level on the output NMOS device.
To improve the ESD level of the output NMOS device, one method is to remove the LDD peak from the output NMOS device. An output NMOS device, which has no LDD peak structure in its drain region, can sustain a far higher ESD level. The traditional method is to add an extra ESD-implantation process step into the CMOS process flow with an additional mask layer to make the output NMOS device having no LDD peak structure. The process of making such an NMOS device without LDD peak structure had been reported in some US patents, which are listed in references [1-7] below.
One typical method of such prior art is shown in FIG. 1 which is a flowchart of a process referred to herein as “the Prior Art I” process. FIGS. 2A-2H show cross-sectional views of the process flow of the Prior Art I process of FIG. 1. In FIGS. 2A-2H, the ESD protection devices are shown as the left-hand portions of the drawings and the internal devices are shown as the right-hand portions of the drawings.
The first step is to provide a substrate with a silicon oxide layer. The next step is to form a gate-oxide layer and a gate electrode layer of doped conductive polysilicon (poly) that is patterned into gate electrodes. That is followed by a self-aligned LDD implantation aside from the gate electrodes. A Heavily Doped ESD Implantation follows. Then cover with a Low-Temperature Oxide (LTO) and form sidewall spacers adjacent to the gate electrodes followed by a CMOS N+ Diffusion Implantation step. A CMOS P+ Diffusion Implantation step follows. A CVD LTO process deposits silicon oxide followed by contact hole etching.
FIG. 2A shows a cross-sectional views of a silicon semiconductor substrate in which a P-well doped with P type dopant has been formed with FOX (field oxide) regions at each end of an ESD Protection Device on the left and an Internal device formed on the right with intermediate portions of the device missing as indicated by the break-away lines in the intermediate FOX regions.
FIG. 2B shows the device of FIG. 2A after forming of a forming of a gate oxide layer, a poly gate electrode layer, a first photoresist mask PR and patterning of the gate electrode stack.
FIG. 2C shows an N− LDD implantation into the product of FIG. 2B aside from peripheral areas including the FOX regions which are protected by a second photoresist mask.
FIG. 2D shows the device of FIG. 2C after the heavy N+ doping ESD protection device implantation of the N+ drain/source (D/S) regions of the ESD protection devices where a third photoresist mask protects the Internal Device plus areas aside from the drain/source regions and the gate electrode stacks including the FOX regions and the entire internal device.
The additional ESD protection device implantation, as shown in FIG. 2D, is added into the process flow with one additional mask layer to form the NMOS without LDD peak structure. Such ESD protection device implantation is done before the formation of sidewall spacers on the gate oxide which follow as shown in FIG. 2E.
FIG. 2E shows the device of FIG. 2D after forming of sidewall spacers on the sidewalls of all of the gate electrode stacks.
FIG. 2F shows the device of FIG. 2E after heavy N+ doping for the N+ D/S diffusion of the internal devices aside from the ESD protection device and peripheral areas including the FOX regions which are protected by a fourth photoresist mask.
FIG. 2G shows the device of FIG. 2F after the doping of a set of P+ diffusions into P+ doped regions between the D/S regions and the FOX regions which are protected by a fifth photoresist mask.
FIG. 2H shows the device of FIG. 2G after a contact hole etching step of forming contact holes CH to the P+ diffusions and the D/S regions.
The LDD peak in the ESD protection device has been covered by the implanting with an extra N+ implantation. The ESD robustness degradation due to the LDD peak in the NMOS structure can be overcome. Thus the ESD level of the ESD protection device can be improved.
Another method for improving the ESD level of the NMOS with LDD peak structure is to generate a low-breakdown-voltage junction rather than through the LDD peak structure. The process for making such an NMOS device with a lower-breakdown-voltage junction is reported in some U.S. patents [8-11].
FIG. 3 is a flow chart of a typical method of such prior art referred to herein as “Prior Art II” [8]. In the flowchart shown in FIG. 3, (Prior Art II) the method illustrated is a variation of the process of FIG. 1. The flow starts by providing a substrate with a FOX oxide layer which is patterned as FOX regions as described above. Then form a gate-oxide and gate-poly as described above. Then perform a LDD Implantation as described above. The process is different at this stage as the next steps are to perform Cover Low-Temperature Oxide (LTO) and Form Sidewall Spacer steps. Next perform N+ Diffusion Implantation, the P+ Diffusion Implantation steps. Next perform the steps of CVD LTO and Etching of Contact Holes. Finally, the step is to perform an ESD implantation to reduce junction breakdown voltage at the end of the process. The process of FIG. 3 is shown in detail in FIGS. 4A-4H which shown the typical step-by-step process flow of Prior Art II [8].
FIGS. 4A-4H show the cross-sectional views of step-by-step the process flow of Prior Art II. In those cross-sectional views, the left-hand portions of the drawings show the ESD protection devices and the right-hand portions of the drawings show the internal devices.
FIG. 4A shows a cross-sectional views of a silicon semiconductor substrate in which a P-well doped with P type dopant has been formed with FOX (field oxide) regions at each end of an ESD Protection Device on the left and an Internal device formed on the right with intermediate portions of the device missing as indicated by the break-away lines in the intermediate FOX regions.
FIG. 4B shows the device of FIG. 4A after forming of a gate oxide layer, a poly gate electrode layer, a first photoresist mask and patterning of the gate electrode stack.
FIG. 4C shows an −LDD implantation into the product of FIG. 4B aside from peripheral areas including the FOX regions which are protected by a second photoresist mask.
FIG. 4D shows the device of FIG. 4C after forming of sidewall spacers on the sidewalls of all of the gate electrode stacks which is different from the process of FIGS. 2A-2H.
FIG. 4E shows the device of FIG. 4D after the heavy N+ doping ESD Protection device and Internal Device implantation of the N+ drain/source (D/S) regions of the ESD protection devices where a third photoresist mask protects the areas aside from the drain/source regions and the gate electrode stacks, including the FOX regions.
FIG. 4F shows the device of FIG. 4E after the doping of a set of P+ diffusions into P+ doped regions between the D/S regions and the FOX regions which are protected by a fourth photoresist mask.
FIG. 4G shows the device of FIG. 4F after a contact hole etching step for forming contact holes to the P+ diffusions and the D/S regions.
FIG. 4H shows the device of FIG. 4G after an ESD protection device implantation with P-type impurity is implanted deeply into the bottom of drain contact holes to reduce the junction breakdown voltage under the drain contact. The extra ESD implantation is added after the contact etching steps, where the ESD implantation region in only located at the center of the drain region including the junction under the drain contact. A fifth photoresist mask covers the internal device as well as the FOX and P+ diffusion contact holes in the ESD protection device.
In FIG. 4H, the ESD implantation is located at the junction under the drain contact to reduce its breakdown voltage. The junction breakdown voltage is dependent on the doping concentrations of the P-type and N-type diffusions around the P-N junction.
The junction region with the ESD protection device implantation of FIG. 4H has a lower breakdown voltage. While the ESD voltage is conducted to the drain of the output NMOS device which is connected to the output pad, the junction region with a lower breakdown voltage can be broken first to bypass the ESD current into the P-well or the substrate. The ESD current is discharged far away from the LDD peak structure and the surface channel, as well as the substrate/well has a large volume to dissipate the heat generated by the ESD current, so the ESD protection devices can sustain a far higher ESD stress.
Generally, the output buffer is used as the ESD protection devices also. To make the output NMOS device with a lower junction breakdown voltage, it needs an extra mask layer and some additional process steps adding into the CMOS process flow. With such methods, the drain breakdown voltage reduces to a lower voltage level. If the output NMOS device in the tri-state condition must sustain high voltage input signals on the pad, the lower junction breakdown voltage due to the additional ESD implantation may cause an unexpected leakage current from the output pad to ground through the low-breakdown junction in the NMOS device.
ESD (electrostatic discharge) damage has become a main reliability concern on the IC (integrated circuit) products. Especially, while the CMOS technology is developed into the deep-submicron regime, the scaled-down MOS devices and thinner gate oxide become more vulnerable to ESD stress. For general industrial specification, the input and output pins of the IC products have to sustain the human-body-model ESD stress of above 2000V. Thus, the ESD protection circuits have to be placed around the input and output pads of the IC devices to protect the IC devices against the ESD damage.
In the output buffers of CMOS IC devices, the output NMOS/PMOS devices are often designed with large device dimensions W/L (Width/Length) to provide the required driving current to the external loads. The large-size output NMOS/PMOS devices also work as the ESD-protection devices to protect themselves. For example, in a 0.35 μm CMOS process, an output NMOS device with a device dimension of W/L=300/0.5 (μm/μm) can sustain the ESD level of greater than 2000V. However, such an NMOS device must be drawn by following the specified ESD design rules in the 0.35 μm CMOS process to sustain a high ESD level. One of the effective methods for improving the ESD level of the output NMOS device and PMOS device is the ESD implantation step.
The device structure of an output NMOS device is drawn in FIG. 7, whereas its corresponding layout top view is shown in FIG. 8, and its device I-V characteristics are shown in FIG. 9. The output NMOS device is often drawn with a wider spacing SDG in the layout. According to the published papers [12-13], the typical value for this spacing SDG is around 3-5 μm for an NMOS device to sustain a high ESD level. When the NMOS device is stressed by the ESD events with an Over-stress current, the NMOS device enters into its snapback region in its I-V curves, as shown in FIG. 9. The parasitic lateral N-P-N BJT (Bipolar Junction Transistor) in the NMOS device is triggered on to generate the snapback region in the I-V curve of the NMOS device. The maximum current that the parasitic lateral N-P-N BJT in the NMOS device can sustain is defined as the secondary breakdown current, marked as the It2 current in FIG. 9. While the ESD current is higher than the It2 current of an output NMOS device, the NMOS device will be permanently damaged by the ESD current. Thus, the operating region of the output NMOS device to bypass the ESD current is the snapback region of its I-V curve. The different device structures and layout styles cause different It2 current values, even if the NMOS device has the same W/L (Width/Length) device dimension.
In the deep-submicron CMOS technology, the NMOS device (also PMOS device) has the LDD (lightly-doped drain) structure, as shown in FIG. 7, to overcome the hot-carrier effect on the short-channel devices. The LDD structure also generates a peak structure at the drain region, which closes to the surface channel. This is the device structure shown in FIG. 1 and the ESD current path shown in FIG. 4.
When such an NMOS device is stressed by a positive ESD voltage, the ESD current is focused and discharged through the LDD peak in the NMOS device structure. The ESD current path on the NMOS device with LDD structure is drawn in FIG. 10. The ESD current is conducted into the drain region through the drain contact, and then conducted to the LDD peak. Because the LDD peak is the nearest region close to the grounded source, the first breakdown on the drain of the NMOS device happens at this LDD peak region. The LDD peak region often has a far shallower junction depth (about 0.02 μm), as compared to the drain N+ diffusion region (about 0.2 μm). The ESD current discharging path along the NMOS device with LDD peak is shown by the line with arrows in FIG. 10. Thus, the LDD region with a far shallower junction depth and diffusion volume is easily damaged by the ESD current to cause a far lower ESD level on the output NMOS device.
To improve the ESD level of the output NMOS device, one method is to remove the LDD peak from the output NMOS device. An output NMOS device, which has no LDD peak structure in its drain region, can sustain a far higher ESD level. The traditional method is to add an extra ESD-implantation step into the CMOS process flow with an additional mask layer to make the output NMOS device having no LDD peak structure, as that shown in FIG. 11. The typical top view of layout to make the NMOS device without LDD peak structure is drawn in FIG. 12. The additional ESD implantation is added into the process flow with at least one additional mask layer to mask the NMOS device without LDD peak structure. Such ESD implantation can be done before or after the formation of sidewall spacer on the gate oxide. The methods for making such an NMOS device without LDD peak structure was reported in some US patents [1-7]. In FIG. 11, the LDD peak in the NMOS device has been covered or removed by the ESD implantation with extra N+ region (the region GR in FIG. 11). The ESD degradation due to the LDD peak in the NMOS device structure can be overcome, thus the ESD level of the output NMOS device can be restored to a higher level with a reasonable spacing from drain contact to the poly gate edge in the layout.
Another method for improving ESD level of an NMOS device with an LDD peak structure is to generate a low-breakdown-voltage junction in the drain diffusion; whereby the ESD current is discharged through the low-breakdown-voltage junction rather than through the LDD peak structure. Such methods are illustrated in FIG. 13 and FIG. 14. The layout for realization of such a method is drawn in FIG. 15, where the ESD implantation region is located only at the center of the drain region including the junction under the drain contact.
In FIG. 13, a high concentration of an N++ dopant material is implanted around the junction under the drain contact to reduce the breakdown voltage around this junction region.
In FIG. 14, a high concentration of a P+ dopant material is implanted around the junction under the drain contact to reduce the breakdown voltage around this junction region. From the semiconductor physics theory, the P-N junction with a higher doping concentration has a lower breakdown voltage. The junction breakdown voltage is dependent on the doping concentrations of the P and N diffusions around the P-N junction. For example in a 0.35 μm 3.3V CMOS process, the original junction breakdown voltage of an output NMOS device with LDD structure is about 8V.
On the other hand, if such an output NMOS device is implanted with the P+ (boron) dopant material as that shown in FIG. 14, the junction breakdown voltage is reduced to only about 6V. The junction region with such ESD implantation (FIG. 13 or FIG. 14) has a lower breakdown voltage. When an ESD voltage is applied to the drain of the output NMOS device which is connected to the output pad, the junction region with a lower breakdown voltage can be broken first to bypass the ESD current into the P-well (or substrate). The ESD current is discharged far away from the LDD peak structure and the surface channel, as well as the substrate/well which has a large volume to dissipate the heat generated by the ESD current. Thus the output NMOS device can sustain a far higher ESD stress. To make a lower junction breakdown voltage output NMOS device, there is a requirement of adding an extra mask layer needs and some additional steps to the CMOS process flow. Steps for making such an NMOS device with a lower breakdown-voltage junction were reported in some US patents, which are listed in [8-11]. With such methods, drain breakdown voltage is reduced to a lower voltage level. If the output NMOS device in the tri-state condition must sustain a high voltage on the pad, the lower junction breakdown voltage due to the additional ESD implantation may causes the unexpected leakage current from the output pad to ground through the low-breakdown junction in the NMOS device.
The typical circuit design for the 3/5V tolerant I/O pad is shown in FIG. 16, where the output PMOS device Mp1 has a self-biased N-well to avoid the parasitic diode connection from the pad to VDD (3.3V). The output NMOS device has a stacked structure with Mn1 and Mn2. The gate of Mn1 is connected to VDD (3.3V) to avoid the gate-oxide wearout issue due to high voltage across the gates of Mn1 and Mn2 in the deep-submicron CMOS process with thinner gate oxide thickness. While the input signal from the pad has a 5V voltage level, the gate of Mn2 and Mp1 is biased by the predriver circuits at the voltage levels which can turn off the Mn2 and Mp1 to keep the output buffer off during operation in the tri-state condition.
The high-voltage input signal is conducted to the internal circuits through the RESD and the NMOS device Mn3. The NMOS device Mn3 is used to clamp the voltage level that reaches to the thinner gate oxide of the input circuits without the gate-oxide wearout issue. Such a circuit design is typically used in the CMOS IC devices those have the 3.3V VDD power supply but have to access the input signals with 5V voltage level. If the ESD implantation method to generate a lower junction breakdown voltage at the drain region is used on the output Mn1 and Mn2 devices to improve their ESD levels, the lower breakdown-voltage drain junction may cause a higher leakage current from the I/O pad to ground through the off-state Mn1 device. The junction breakdown voltage of the output NMOS device in a 0.35 μm 3.3V CMOS process is typically about 6V with the additional ESD implantation. Such an NMOS device with a lower junction breakdown voltage biased at 5V voltage level often has a significant leakage current greater than 1 μA, because the lower junction breakdown voltage (about 6V) is close to the bias voltage level. Thus, it is not safe enough to be used widely in the high-voltage-tolerant I/O circuits with the consideration on the process variation.